This invention relates to a wiring pattern or a wiring arrangement of a semiconductor integrated circuit, particularly to an electrode pad of the wiring pattern.
In general, a semiconductor integrated circuit is constructed by forming a plurality of circuit elements, such as transistors and resistors, on a semiconductor chip and wiring the circuit elements to form an electrical circuit. The wiring is formed by a metal or silicon wiring layer. At some portions of the metal wiring layer such as power supplying portions and input and output portions which need connection to an external circuit or element, electrode pads are formed and connected to a lead provided on package by fine metal wire.
An electrical characteristic checking of such integrated circuit is performed by observing a voltage or a current between two electrode pads or two leads. It is, however, difficult to check the electrical characteristics of individual circuit elements, particularly such elements forming a feed-back loop requiring no external elements.
Further, semiconductor integrated circuit devices are manufactured in the following manner. That is, a plurality of integrated circuits are formed on one semiconductor wafer, and the wafer is divided into individual integrated circuit chips. A chip is fixed in a package, and the electrical connection between electrode pads of the chip and leads of the package are formed by wire-bonding, and then the package is hermetically sealed. In such manufacturing process, it is preferable in view of cost saving to find and remove defective chips in an earlier step, because the additional manufacturing cost can be saved.
Now, the checking of D.C. characteristics can be conventionally achieved for a plurality of integrated circuits on one semiconductor wafer, while that of A.C. characteristics such as noise figure (NF) cannot be examined before chips are housed in the packages. This is because the electrical characteristics of the integrated circuit on the wafer are easily affected by external noise and precise electrical data cannot be obtained due to large junction capacitance and because a longer time period for checking is required than the D.C. characteristic checking. Instead of A.C. characteristic checking, it is possible to estimate the A.C. characteristics by checking the D.C. characteristics of individual circuit elements. That is, however, also impossible on the conventional integrated circuit because the individual element checking is impossible.